Integrated circuit design is constantly being scaled down in pursuit of faster circuit operation and lower power consumption. Scaled dimensions in a circuit design generally requires attendant changes in fabrication processing.
A basic building block of integrated circuits is the thin film transistor (TFT). As is known in the art, the transistor typically includes a gate electrode separated from a semiconductor layer or substrate by a thin gate dielectric material. One area in which process control is particularly critical is the fabrication of transistor gate dielectrics. In the pursuit of ever faster and more efficient circuits, semiconductor designs are continually scaled down with each product generation. Transistor switching time plays a large role in the pursuit of faster circuit operation. Switching time, in turn, can be reduced by reducing the channel length of the transistors. In order to realize maximum improvements in transistor performance, vertical dimensions should be scaled along with horizontal dimensions. Accordingly, effective gate dielectric thickness, junction depth, etc. will all decrease with future generation integrated circuits.
Conventional gate dielectrics are formed of high quality silicon dioxide and are typically referred to as “gate oxide” layers. Ultra thin gate oxides (e.g., less than 5 nm), however, have been found to exhibit high defect densities, including pinholes, charge trapping states, and susceptibility to hot carrier injection effects. Such high defect densities lead to leakage currents through the gate dielectric and rapid device breakdown unacceptable for circuit designs with less than 0.25 μm gate spacing, i.e., sub-quarter-micron technology. Even if the integrity of the oxide is perfectly maintained, quantum-mechanical effects set fundamental limits on the scaling of gate oxide due to quantum tunneling effects.
Theoretically, incorporating materials of higher dielectric constant into the gate dielectric opens the door to further device scaling. Due to higher dielectric constant, many materials can exhibit the same capacitance as a thinner silicon dioxide layer, such that a lower equivalent oxide thickness (EOT) can be achieved without tunnel-limited behavior. Silicon nitride (Si3N4), for example, has a higher dielectric constant (“k value”) than SiO2 and also demonstrates good diffusion barrier properties, resisting boron penetration. More exotic “high k” materials with even higher dielectric constants, including aluminum oxide (Al2O3), zirconium oxide (ZrO2), hafnium oxide (HfO2), barium strontium titanate (BST), strontium bismuth tantalate (SBT), tantalum oxide (Ta2O5), etc., are also being investigated to allow further device scaling.
Recent developments on another front in transistor design have focused on increasing the electrical carrier mobility in the single-crystal semiconductor material (substrate or epitaxial layer) in which the transistors are formed. One method of increasing carrier mobility is to produce strained layers, such as strained silicon over relaxed silicon germanium.
Pure germanium also exhibits greater carrier mobility than silicon, whether or not the germanium crystal structure is strained. Until recently, interest in germanium has been limited, in part, by the inability to grow consistent, high quality oxides from the surface, such that gate dielectrics would have to be deposited. Since oxides thermally or chemically grown from silicon exhibited the highest quality and most consistent thickness, a preference for silicon dioxide gate dielectrics has until recently dictated a preference for silicon over germanium as the semiconductor material of choice.
The growing preference for deposited high k dielectrics, rather than grown oxides, now has the potential to obviate the most significant disadvantage to germanium as the semiconductor base layer for transistor. The possibility for high carrier mobility in germanium combined with scaled dimensions enabled by high k dielectrics is very attractive for future integrated circuit design.
Despite significant advantages for these materials, both germanium and high k materials raise their own integration challenges. Accordingly, significant advances are required before production worthy methods are available for integrating these new materials into fabrication process flows.